Informatics Publishing Limited

Kakarla Hari Kishore ¹, Pavuluri Srinivas ¹, Fazal Noorbasha ¹, Atluri Jhansi ¹

Affiliations
1 VLSI Research Group, Department of ECE, KL University, Vaddeswaram, Guntur (Dist.), AP-522502, IN

Abstract

In these paper implementing fault detection and repair of word redundancy MBISR (Memory Built In Self Repair) using March SS and march RAW algorithms. A new micro coded BIST architecture is presented here which is capable of employing new test algorithms like March SS and March RAW that have been developed for coverage of some recently developed static and dynamic fault models. The same hardware has been used to implement other new March algorithms. This requires just changing the Instruction storage unit, or the instruction codes and sequence inside the instruction storage unit. The instruction storage unit is used to store predetermined test pattern. The simulation results have shown that the micro-coded MBIST architecture described here is an effective testing method to test embedded memories as it provides a flexible approach and better fault coverage. Just as March SS, any other new march algorithm can also be implemented using the same BIST hardware by changing the instructions in the microcode storage unit, without the need to redesign the entire circuitry. The word redundancy uses spare words in place of spare rows and columns. This repair mechanism avoids lengthy redundancy calculations as suggested by some other authors in their works as it stores faulty location addresses immediately supporting on-the-fly fault repair. Moreover, it can be interfaced easily with existing MBIST logic.

Keywords

Built-In Self Test (BIST), Built-In Self Repair (BISR), Memory Built-In Self Test (MBIST), Micro Coded MBIST, Memory Built-In Self Repair (MBISR).

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Fazal Noorbasha ¹, Shaik Moulali ¹, S. Dayasagar Chowdary ¹

Affiliations
1 Department of Electronics & Communication, KL University, Guntur (District), AP, IN

Abstract

In today‘s Integrated Circuits (ICs), Built-In-Self Test (BIST) is becoming increasingly important as designs become more and more complicated. BIST is beneficial in many ways:First, it can reduce dependency on external Automatic Test Equipment (ATE). In addition, BIST can provide at speed, in system testing of the Circuit-Under-Test (CUT). This is crucial to the quality component of testing. BIST can overcome pin limitations due to packaging, make efficient use of available extra chip area, and provide more detailed information about the faults present. On a very basic level, BIST needs a stimulus (the Test Pattern Generator-TPG), a circuit to be tested (CUT) and a way to analyze the results (ORA). Additionally, there may be compression schemes for the TPG and the ORA. A 64 bit RISC processor with limited functionality will design with an architecture that supports BIST. The ALU is analyzed and an exhaustive set of test patterns will develop. Here clock gating technique is used for reducing the power consumption of the design. Some of these applications include vending machines, bottling plants, control of robotic movements, and automatic teller machine (ATM). Cadence tool is used for synthesis and Xilinx ISE is used for simulation.

Keywords

RISC, BIST, BISR, Memory, Clock Gating.

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Fazal Noorbasha ¹, S. Dayasagar Chowdary ¹, K. Hari Kishore ¹, Shaik Moulali ¹

Affiliations
1 Department of Electronics & Communication, KL University, Guntur District, IN

Abstract

LFSR's are the functional building blocks of circuits like the pseudo-random noise (PN) code generator that are commonly used in Code Division Multiple Access (CDMA) systems. This application note describes two implementations of an SR4 (Shift Register) primitive for area-efficient designs LFSR using the encryption and decryption algorithms using XOR gate in 180nm for less area and low power methodologies for ASIC designs using Cadence design tools. The unusual sequence of values generated by an LFSR can be gainfully employed in the encryption and decryption of data. That makes the cryptography quite easy and useful for longer bit lengths. A stream of data bits can be encrypted and decrypted by XOR-ing them with output from an identical LFSR's which finds the certain applications like Radio and visual broad casting schemes, Internet and Wireless communications. This work mainly concentrates on the 4 bit random number that uses for encryption that is mainly works faster clock rates of  100MHz, which finds the application in wireless networks.

Keywords

LFSR, Low Power, CDMA, Pseudo Random Noise Generator, XOR, Encryption and Decryption.

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Fazal Noorbasha ¹, Ch. Hemanth ¹, A. Sivasairam ¹, V. Vijaya Raju ¹

Affiliations
1 VLSI Research Group, Department of ECE, KL University, Vaddeswaram, Guntur (Dist.), AP, IN

Abstract

The increasing growth of sub-micron technology has resulted in the difficulty of VLSI testing. Test and design for testability are recognized today as critical to a successful design. BIST is a design technique that allows a circuit to test itself. The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production. Due to the randomness properties of Linear Feedback Shift Registers (LFSR), this requires very little hardware overhead. However conventional LFSR fall short in fault coverage. In order to improve the fault coverage we introduce an improved LFSR called Multi Test Pattern Sequence LFSR (MTPS LFSR). In this paper the structure of this improvised LFSR is described. This paper also focuses on the implementation of low power MTPSLFSR using various CMOS logics. This paper discusses architectures in terms of the hardware implementation, using pass transistor logic CMOS layout and power consumption, using 90nm CMOS layout Technology. Along with this it also explains about fault coverage improvement by using MTPS LFSR.

Keywords

MTPS LFSR, ORA, CUT, Pass Transistor, 90nm CMOS Technology.

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K. Hari Kishore ¹, Fazal Noorbasha ², Habibulla Khan ³, Asiya Begum ¹, Y. Rajasekhar Reddy , K. Anil Kumar

Affiliations
1 Department of ECE, KL University, Vijayawada, A.P, IN
2 Department of Electronics and Communication Engineering, KL University, Guntur, Andhra Pradesh, IN
3 Department of Electronics & Communication Engineering, KL University, Vijayawada, AP, IN

Abstract

Any VLSI circuit is composed of the very basic unit that is the multiplier. As technology is increasing day by day many new designs are being evolved. As the design becomes bigger more will be the delay in it. If the delay in the basic unit that is multiplier can be decreased then the overall delay in the new designs can be effectively alleviated. There are many multipliers designed so far in the field of VLSI using different methods for its implementation. This paper presents implementation of a Modified Booth multiplier. So far many Modified Booth multipliers are implemented. In all the methods for generating the partial products 'negi' the extra partial product bit is used due to which number of partial products generated will be N/2+1. If this 'negi' bit in the partial products can be avoided and efficient way for generating 2's complement of negative partial product is used which generates conversion signals, and then the number of partial products will decrease to N/2. For addition of partial products the design uses the 4:2 compressors to reduce the complexity in the circuit involved.

Keywords

Modified Booth Multiplier, Partial Product, Conversion Signal, 4:2 Compressors.

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T. Narendra Babu ¹, Fazal Noorbasha ¹, M. Harita ², N. Tejashree ², K. Vamsi Krishna ²

Affiliations
1 Department of ECE, K L University, Vaddeswaram, Guntur - 522502, Andra Pradesh, IN
2 Department of ECM, K L University, Vaddeswaram, Guntur - 522502, Andra Pradesh, IN

Abstract

Background: Our main objective is to improve the error detection and correction capability using orthogonal codes with high security and speed. Statistical Analysis: In order to achieve high speed and security for error detection and correction, we have used cryptography technique. The concept of segmentation is specifically used, as it gives highly secured signal and also reduces the time complexity. Previous study incorporates mapping technique for error detection and correction. Our proposed methodology uses two decoders in place of mapping at the receiver end. This eases the performance and decreases the clock pulses. Findings: The proposed technique will send the k-bit data to encoders and it gets converted into orthogonal codes. The data is then encrypted using encryptor which consists of LFSR. The data is then sent to the receiver and then original data is retrieved using the decoders at the receiver. The multiple bit error correction can be done up to (n/4-1) bits. Here we have compared the delays for 4-bit, 5-bit, 6-bit, 7-bit, 8-bit data. After comparing our technique with the previous study we have found out that the delay time is gradually reduced. Our proposed work is done in n/2+1 comparison, where n represents the bit length of orthogonal codes. Hence this technique achieves 100% multiple bit error detection and error correction rate in the received signal. This technique is simulated in Xilinx software and implement using Field Programmable Gate Array (FPGA). Application/Improvements: This technique can be used for efficient transmission of data in the networks. There is also a wide scope for improvement to limit the bandwidth.

Keywords

Comparator, Error Detection and Correction, FPGA, LFSR, Orthogonal Codes.

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Fazal Noorbasha ¹, K. Sundar Teja ¹, Bhavana Endreddy ¹, Nikitha Adidela ¹, Ch. Naga Pavan Kumar ¹

Affiliations
1 Department of ECE, K L University, Vaddeswaram, Guntur - 522502, Andhra Pradesh, IN

Abstract

Objectives: This paper presents the implementation of cryptography algorithm with adders and subtractor. Security of data has become most challenging aspects in the network applications, internet and data communication systems. Cryptography gives the better solution as it provides authentication, integrity protection and privacy by converting the plain text into the cipher form using different encryption and decryption techniques. Methods/Statistical Analysis: For the purpose of secured communication, certain cryptographic techniques and error detection correction techniques are used. The encryption and decryption as well as error detection and correction part is done by hamming code algorithm. For high security and circuit optimization purpose, we have introduced different adder and subtractor circuits in the hamming code cryptography process. Findings: According to our simulation results, our new method can work quite well. We achieved low-power and less delay process because of adder’s structure modifications. Applications/Improvements: This proposed method is useful in any data communication systems and also in military applications.

Keywords

Adder, Cryptography, Decryption, Encryption, Hamming Code, Subtractor

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